Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge storage nodes (e.g., floating gates or trapping layers) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, cellular telephones, and removable memory modules.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line. A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. The select gates are typically field-effect transistors. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
The memory array is accessed by a row decoder activating a row of memory cells by selecting the word line connected to (and, in some cases, formed by) a control gate of a memory cell. In addition, the word lines connected to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the column bit line to the source line through each NAND string via the corresponding select gates, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines.
For some applications, flash memory stores a single bit per cell. Each cell is characterized by a specific threshold voltage, which is sometimes referred to as the Vt level. Within each cell, two or more possible Vt levels exist. These Vt levels are controlled by the amount of charge that is programmed or stored on the floating gate. For some NAND architectures, for example, a memory cell might have a Vt level greater than zero in a programmed (e.g., logic zero) state and a Vt level less than zero in an erase (e.g., logic one) state.
Memory cells are typically programmed using program/erase cycles, e.g., where the memory cells are first erased and subsequently programmed. For a NAND array, a block of memory cells is typically erased by grounding all of the word lines in the block and applying an erase voltage to a semiconductor substrate on which the memory cells are formed, and thus to the channels of the memory cells, to remove the charge from the floating gates. More specifically, the charge is removed through Fowler-Nordheim tunneling of electrons from the floating gate to the channel, resulting in an Vt level typically less than zero in an erased state.
Programming typically involves applying a program voltage to one or more selected word lines and thus to the control gate of each memory cell coupled to the one or more selected word lines, regardless of whether a memory cell is targeted or untargeted for programming. While the program voltage is applied to the one or more selected word lines, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, to charge the floating gates. More specifically, the floating gates are typically charged through direct injection or Fowler-Nordheim tunneling of electrons from the channel to the floating gate, resulting in a Vt level typically greater than zero in a programmed state. In addition, a potential, such as a ground potential, is typically applied to the bit lines coupled to NAND strings containing memory cells targeted for programming and an inhibit voltage is typically applied to bit lines coupled NAND strings containing memory cells that are not targeted for programming.
Programming is sometimes accomplished by applying the program voltage to the one or more selected word lines and applying the ground potential to every other bit line at a time, such as the even-numbered bit lines coupled to even-numbered NAND strings followed by the odd-numbered bit lines coupled to odd-numbered NAND strings. This means that the targeted memory cells in the even-numbered NAND strings are programmed first followed by the targeted memory cells in the odd-numbered NAND strings.
The subsequent programming of the targeted memory cells in the odd-numbered NAND strings generally involves applying a program voltage to targeted memory cells in odd-numbered NAND strings on either side of the previously programmed memory cells in an even-numbered NAND string. However, the subsequently programmed memory cells in the odd-numbered NAND strings will generally tend to pull up the Vt level of the previously programmed memory cells in the even-numbered NAND string due to capacitive coupling between the floating gates of the subsequently programmed memory cells in the odd-numbered NAND strings and the previously programmed memory cells in the even-numbered NAND string.
The increase in the Vt level may act to cause problems in that the increase in the program Vt level can change the data value of a programmed cell. For example, multi-level memory cells generally have different program Vt level ranges, e.g., of 200 mV for each range, with each range corresponding to a distinct data state, thereby representing different data values or bit patterns, and a capacitive-coupling-induced increase in the Vt level could change those data values.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing bit line configurations.